The present invention relates to a switching device or a transfer processing apparatus for performing the flow control of multiple packet types and each of the packet types and the transfer of the packets according to a common protocol specifying ordering rules among the packet types, and more particularly to a switch circuit comprising three or more ports.
PCI Express is a name of a bus which is standardized as a succeeding standard of the PCI so as to be a standard expansion bus available for the computers in general and particularly a data transfer bus which is characterized by high-speed data transfer and serial transfer which enable full-duplex transmission at 2.5 Gbps or more in one direction.
The PCI Express covers mainly three types of packets such as Posted, NonPosted and Completion. The Posted is mainly used to reply to a write request, the NonPosted is mainly used to reply to a read request, and the Completion is used to reply to a read request.
To transfer packets, a transmitter RAM and a receiver RAM are used. To transmit the packets from the transmitter RAM to a communication path, flow control is performed to recognize the available state of the receiver RAM on a part of the transmitting side and to control the packet transmission timing in order to prevent the receiver RAM of a destination device from overflowing. The receiving side notifies the remainder capacity of the receiver RAM to the transmitting side when the packet is read from the transmitter RAM or on a timely basis. The transmitting side compares the remainder capacity of the receiver RAM notified from the receiving side with a transmission-scheduled packet size, and if the remainder capacity of the receiver RAM is smaller than the transmission-scheduled packets, the packet transfer is waited until the receiver RAM has an available space. By controlling as described above, the receiver RAM is prevented from overflowing.
In a case where the flow control is performed for each packet type, the ordering rules specify whether or not a packet type, which is held in a waiting state by the flow control, can be overtaken by the following packet type. Typical examples include “Posted must overtake another NonPosted” and “NonPosted should not overtake Posted.” They are used in order to prevent a deadlock or to keep consistency of data.
For example, it may be assumed that a write is performed from the CPU to the memory, a read is performed from the CPU to the memory, and comparison is performed between the write data previously performed and the read data returned from the memory. If a write request Posted from the CPU is overtaken by a read request Non-Posted, the comparison cannot be performed properly. To prevent such a situation, the ordering rules are specified between the packets.
In a switch circuit comprising three or more ports for performing the transfer of packets according to the PCI Express protocol, a packet type which is in a transfer waiting state according to the flow control might not be overtaken by another packet type according to the ordering rules. Therefore, another packet type, which is not directly subjected to a transfer waiting state by the flow control, also falls in a transfer waiting state.
Where the transfer waiting state is caused by the flow control, the flow control to one packet type having a particular device as a destination has an effect on another packet having the same device as a destination and also on a packet having another device as a destination. Thus, the switch circuit as a whole is clogged because of the packets which are made to be in a transfer waiting state by the flow control.
As a method of preventing the clogging of the switch circuit as a whole due to the above-described packet transfer waiting state, there is a method that when the packets received through individual ports are transferred to another port, the packets are temporarily stored in an intermediate RAM. For example, JP-A-07-264242 has proposed a method that a low-speed large-scale RAM and a high-speed small-scale RAM are adopted as the intermediate RAMs to improve packet transfer efficiency. As another method, provision of a transfer data path in the switch circuit for each packet type allows to transfer without an influence of another packet type.
JP-A-2001-320385 has proposed a method that the packets received by a receiver unit according to the PCI standard are stored in a RAM according to each priority determined for each packet type, a transmission request is sent to the transmitter unit, the replay of a transmission permission signal from the transmitter unit is checked, and the packets are transferred. Use of this method enables to transfer a high priority packet type with a transmission request cancelled if the transmission permission signal to a low priority packet type is not replied.
JP-A-2003-18188 has proposed a method that packets are divided depending on packet types and stored in RAMs, and the priority sequences of the individual RAM outputs are changed by a logical flow control mechanism, so that when a high priority packet is made to wait for transfer, the transfer of a packet having the same destination as that of the packet in a transfer waiting state and a packet addressed to another device is free from any influence.
But, when the switch circuit has therein the intermediate RAM as shown in FIG. 9 of the above-described related art, e.g., JP-A-07-264242, the clogging of the switch circuit due to the flow control and the ordering rule can be prevented, but there is a problem that the transfer speed of the switch circuit becomes slow at all times because of routing through the intermediate RAM even if there is no occurrence of the transfer waiting by the flow control in comparison with a case not being routed via the intermediate RAM.
Where a transfer data path within the switch circuit shown in FIG. 10 is provided for each packet type, the packets can be transferred without being influenced by the transfer waiting state of another packet type but there is a possibility that the order of the packets transferred to the transmitter RAM of the switch circuit is different from the order of reaching the receiver RAM of the switch circuit. Therefore, it is necessary to manage the arrival sequence of the receiving packets on a part of the transmitter RAM, and an additional control circuit is required.
In either case, the logical scale of the switch circuit becomes large, and the number of ports mountable in a unit area becomes small. Reduction of the logical scale of the switch circuit which tends to have a multiport is an important proposition, and measures are demanded to be taken with the logical scale suppressed.